1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a phase change memory for nonvolatily storing information with a change in a resistance value which is caused by a phase change.
2. Description of the Background Art
A phase change memory carries a current (an amorphous current) for causing an amorphousness over a memory cell constituted by a phase change material to melt the phase change material through resistance heating, then performs cooling to bring an amorphous state, and carries a current (a crystallizing current) for causing a crystallization over the phase change material to anneal the phase change material through the resistance heating, thereby bringing a crystalline state.
Binary information can be selectively written to a memory cell in two states of the phase change material. A state which is once subject to a phase change is not changed at an ordinary temperature. Therefore, it is possible to hold the information nonvolatily.
The phase change memory is a nonvolatile memory which can also be applied to both a memory embedded logic chip and a memory stand-alone chip and has been developed in a strategic location as a memory which succeeds to an existing NOR type flash memory and MONOS (Metal Oxide Nitride Oxide Semiconductor) memory. The MONOS is also referred to as SONOS (Silicon Oxide Nitride Oxide Semiconductor).
The research and development of the phase change memory for carrying out storage and read by conducting the phase change material has already been started in approximately 1970. A decline was caused for a certain period of time. However, a novel developed phase change material (GeSbTe) was successfully applied to an optical disk so that an activity was taken again. As a trigger for recovering an opportunity, a 4 Mbit phase change memory was published by Intel Co., Ltd. in 2002. After that, a large number of semiconductor manufacturers entered the development.
There have been invented a cross point type having no access device to an element, a type using a diode as an access device, a type using an MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) as an access device or a type using a bipolar transistor in a case in which a phase change element is arranged as a memory array.
An example of a phase change memory using the MOSFET as an access device has been described in Y. N. Hwang et. al., “Writing Current Reduction for High-density Phase-change RAM” International Electron Devices Meeting 2003, pp. 893-896 (non-patent document 1).
For a phase change film, a chalcogenide semiconductor film such as GeSbTe (GST) is usually used. An ordinary semiconductor material and process can be applied to the MOSFET serving as the access device and a process for forming and processing, a device isolating film, a wiring layer and an interlayer insulating film.
By taking, as an example, a non-patent document 1, description will be given to the related art.
First of all, FIG. 20 shows a sectional structure of a non-patent document 1.
As shown in FIG. 20, an MOS transistor Q1 for access is provided on a silicon substrate 1 and an interlayer insulating film IL1 is provided to cover the MOS transistor Q1. A plurality of contact plugs CP1 to penetrate the interlayer insulating film IL1 is provided to reach a plurality of diffusion layers 3 disposed in a surface of the silicon substrate 1. A silicide layer SS is provided on the diffusion layer 3 and each contact plug CP1 is actually provided in contact with the silicide layer SS. For convenience, however, an expression of “reach the diffusion layer 3” is used.
The MOS transistor Q1 includes a gate insulating film 4 provided selectively on an active region defined by an isolation insulating film 2, a gate electrode 5 provided on the gate insulating film 4, and the diffusion layer 3 which is provided selectively in the surface of the silicon substrate 1 on the outside of both side surfaces in a direction of a gate length of the gate electrode 5 and serves as a source-drain layer. The gate electrode 5 is extended in a depth direction with respect to the drawing and serves as a word line and is covered with the silicide layer SS. The side surfaces of the gate insulating film 4 and the gate electrode 5 are covered with a sidewall insulating film, which is not shown.
Any of the plurality of contact plugs CP1 which reaches the diffusion layer 3 to be a source layer of the MOS transistor Q1 has an end connected to a source line SL (extended in the depth direction with respect to the drawing) having an end provided on the interlayer insulating film IL1, and the other contact plugs CP1 are connected to a connecting pad PD having an end disposed on the interlayer insulating film IL1. The source line SL and the connecting pad PD are constituted by a first metal wiring (M1).
The source line SL and the connecting pad PD are provided in an interlayer insulating film IL2 disposed on the interlayer insulating film IL1, and an interlayer insulating film IL3 is provided on the interlayer insulating film IL2. A contact plug CP0 is provided to reach the connecting pad PD penetrating the interlayer insulating film IL3, and an end of the contact plug CP0 is directly connected to a lower main surface of a phase change film 20 provided on the interlayer insulating film IL3.
The phase change film 20 is constituted by GST to be a chalcogenide compound based phase change material, an upper electrode 21 is provided on the phase change film 20, and the phase change film 20 and the upper electrode 21 will be referred to as a phase change element PE together.
An interlayer insulating film IL4 is provided on the interlayer insulating film IL3 to cover the phase change film 20 and the upper electrode 21, and a contact plug CP2 is disposed to reach the upper electrode 21 through the interlayer insulating film IL4. The contact plug CP2 has an end connected to a bit line BL provided on the interlayer insulating film IL4. The bit line BL is constituted by a second metal wiring.
With the structure described above, a region surrounded in a broken line in the drawing, that is, a region including a single MOS transistor Q1 and a phase change element PE conducted by turning ON the MOS transistor Q1 constitutes a memory cell MC corresponding to one bit. Two memory cells MCs which are close to each other are constituted to share a single source line and the contact plug CP0 linked thereto.
In a case in which the structure of the memory cell MC shown in FIG. 20 is employed, a distance corresponding to two interlayer insulating films is formed between a first metal wiring (M1) formed in the interlayer insulating film IL2 and a second metal wiring (M2) formed on the interlayer insulating film IL4 in a peripheral circuit region. The reason is that the structure is set to be common to the structure of a memory cell region, resulting in a simplification of a manufacturing process.
More specifically, in the memory cell MC, it is necessary to laminate the interlayer insulating films IL3 and IL4 in order to form a three-stage connecting structure including the contact plug CP0, the phase change element PE and the contact plug CP2 between the connecting pad PD and the second metal wiring M2. Therefore, the peripheral circuit region is also adapted thereto.
As a result, in the peripheral circuit region, a depth of the contact plug (CP2) is increased and a thickness of the interlayer insulating film between the first metal wiring (M1) and the second metal wiring (M2) is increased so that a line capacity is decreased. In particular, this is a serious problem in a embedded chip. More detailed description will be given.
In a memory embedded logic chip (an embedded chip) in which a phase change memory and a logic circuit are provided, a design of the logic circuit (peripheral circuit) is changed corresponding to the structure of a memory cell in order to simplify the manufacturing process. The circuit is usually designed through a computer simulation using a model set obtained by mathematically modeling an MOS transistor characteristic, a wiring resistance and a parasitic capacity. As described above, in the case in which the line capacity is different from that in an existing model set as a result of the adaptation to the structure of the memory cell, it is necessary to modify the model set and to design the circuit again. In a embedded chip in which various products are assumed to be applying destinations, particularly, a cost is increased in respect of a business profit, which is a serious problem.
The problem is caused by disposing the phase change element between the wiring layers. In order to solve the problem, it can be proposed to dispose the phase change element below a lowermost layer wiring.
As an example of the structure in which the phase change element is disposed below the lowermost layer wiring, the structures disclosed in Japanese Patent Application Laid-Open No. 2006-287222 (patent document 1) and 2006-294970 (patent document 2) are taken.
In patent document 1 and patent document 2, a decrease in the line capacity is not recognized as a problem to be solved. However, FIG. 1 in patent document 1 and FIG. 13 in patent document 2 have disclosed a structure in which the phase change element is provided below the lowermost layer wiring. It can be supposed that a drawback of the decrease in the line capacity is not caused by the employment of the structure.
In a case in which the phase change element is provided below the lowermost layer wiring, the phase change element has such a structure that the lowermost layer wiring is interposed between the lower interlayer insulating film and the upper interlayer insulating film which are obtained by dividing the lowermost layer wiring into two upper and lower layers. The lowermost layer wiring is formed on the upper interlayer insulating film and is connected to the upper surface of the phase change element through the contact plug formed in the upper insulating film. Moreover, the lower surface of the phase change element is connected to the diffusion layer formed in the silicon substrate through the contact plug formed in the lower insulating film.
On the other hand, in the peripheral circuit region, the lowermost layer wiring is connected to the diffusion layer formed in the silicon substrate through the contact plug penetrating the lower interlayer insulating film and the upper interlayer insulating film.
However, the employment of the structure causes some new problems which will be described below.
More specifically, as a first problem, the contact plug for connecting the lowermost layer wiring to the semiconductor substrate is excessively deep as discussed in patent document 2. In this case, there are required a process technique and a process device which correspond to a high aspect ratio. A cost is increased and thereby the business profit is damaged.
In FIG. 12 showing patent document 2, there is disclosed a structure in which the lowermost layer wiring and the phase change element are formed in the “same layer”, that is, on the same level. Instead, a degree of difficulty of the process is raised and the number of process steps is increased.
As a second problem, the contact plug (the lower plug) for connecting the lower surface of the phase change element to the semiconductor substrate is deepened and it is hard to reduce a diameter. More specifically, there is generally employed a method of setting the diameter of the lower plug such as the contact plug CP0 in FIG. 20 to be smaller than a standard hole diameter of the contact plug (a diameter of approximately several tens nm), thereby increasing a current density in order to reduce an operating current in the phase change memory. For this purpose, it is desirable that the depth of the plug should be small in respect of the characteristic of dry etching.
In the memory cell MC shown in FIG. 20, the depth of the contact plug CP0 is determined by only the thickness of the interlayer insulating film IL2 for insulating the phase change element PE from the first metal wiring provided thereunder. By setting a process for forming the interlayer insulating film IL2 and the CMP process as a special process to strictly increase precision, therefore, it is possible to form the interlayer insulating film IL2 thinly, thereby reducing the depth of the contact plug CP0 to some degree.
In a case in which the phase change element is disposed below the first metal wiring, however, the interlayer insulating film provided thereunder is to be thicker than at least the height of the gate electrode (word line) in order to cover the MOS transistor. The depth of the contact plug is greater than that of the contact plug CP0 shown in FIG. 20.
As described above, in the conventional memory embedded logic chip in which the phase change memory and the logic circuit are provided, there is a request for disposing the phase change element below the lowermost layer wiring in order to prevent the thickness of the interlayer insulating film between the first metal wiring and the second metal wiring from being increased, resulting in a decrease in the line capacity. In that case, however, the contact plug for connecting the lowermost layer wiring to the semiconductor substrate is excessively deepened so that there are required a process technique and a process device which correspond to a high aspect ratio, resulting in an increase in a cost. Moreover, there is a problem in that the depth of the contact plug for connecting the lower surface of the phase change element to the semiconductor substrate cannot be set to be smaller than the height of the gate electrode (the word line) and it is hard to reduce the diameter of the contact plug, resulting in an increase in an operating current.